DON26BZ05-NV077 TITLE: Multi-Core Parallel Processing for Sensor Fusion Architecture
OUSW (R&E) CRITICAL TECHNOLOGY AREA(S): Quantum and Battlefield Information Dominance (Q-BID)
COMPONENT TECHNOLOGY PRIORITY AREA(S): Advanced Computing and Software
PROJECTED CMMC LEVEL REQUIREMENT: Level 2 (Self)
OBJECTIVE: Investigate and develop an efficient architectural structure/design to optimize sensor fusion algorithms within multi-core processors using parallel processing.
DESCRIPTION: The enhancement of target tracking, situational awareness, and decision-making in manned and autonomous systems is accomplished by fusing data from multiple sensors (homogeneous and heterogeneous). There are many complex issues within the implementation of sensor fusion, including, but not limited to, process latency, overprocessing of redundant data, and the inherent serial nature of current fusion architecture. To alleviate these issues, a prioritization ranking system is implemented to process higher valued tracks/data while dropping others. This forces a trade-off that risks track loss, leading to incomplete tracks and reduced situational awareness for operators in high-workload environment.
The objective is to develop a modular, platform-agnostic sensor fusion architecture that utilizes multi-core parallel processing to optimize data throughput and minimize latency. The system must support the parallel execution of both whole-task and sub-task fusion algorithms across multiple processing cores to maximize hardware utilization. The proposed architecture must demonstrate a significant reduction in process latency without the loss of fused track data or correlation accuracy.
Key requirements include:
Parallelization: Ability to decompose fusion tasks into sub-tasks (spatial-alignment, temporal correlation, and attribute fusion) for concurrent execution.
Track Integrity: Elimination of track loss currently caused by serial processing bottlenecks or aggressive data-prioritization filters.
Latency: Real-time processing capability to support operators decision-making in dynamic, complex environments.
Platform Integration: Size, Weight, and Power (SWaP) for the processing unit should be compatible with 5th-generation or later platforms (typically 0.5 to 1.0 cubic feet and 28V DC power).
Scalability: Design accommodates increasing number of data sources, including, but not limited to:
o AESA Radar
o Distributed Aperture Systems (DAS)
o Electro-Optical Targeting Systems (EOTS)
Work produced in Phase II may become classified. Note: The prospective contractor(s) must be U.S. owned and operated with no foreign influence as defined by 32 U.S.C. § 2004.20 et seq., National Industrial Security Program Executive Agent and Operating Manual, unless acceptable mitigating procedures can and have been implemented and approved by the Defense Counterintelligence and Security Agency (DCSA) formerly Defense Security Service (DSS). The selected contractor and/or subcontractor must be able to acquire and maintain a secret level facility and Personnel Security Clearances. This will allow contractor personnel to perform on advanced phases of this project as set forth by DCSA and NAVAIR in order to gain access to classified information pertaining to the national defense of the United States and its allies; this will be an inherent requirement. The selected company will be required to safeguard classified material during the advanced phases of this contract IAW the National Industrial Security Program Operating Manual (NISPOM), which can be found at Title 32, Part 2004.20 of the Code of Federal Regulations.
PHASE I: Focus on the architectural definition and high-fidelity modeling of a multi-core parallel processing sensor fusion engine. The approach consists of three primary tasks:
Architecture Design: Define a scalable fusion framework that decomposes the serial bottlenecks into parallelizable sub-tasks. This design will specifically address the integration of data streams within the specified SWaP constraints of a tactical processing unit.
Modeling and Simulation (M&S): Develop a discrete-event simulation environment to provide an initial assessment of throughput, latency, and track correlation accuracy. The simulated environment will assess and compare the proposed parallel architecture against current serial benchmarks to quantify performance gains.
Feasibility Validation: Establish the mapping of fusion sub-tasks to physical CPU/GPU/FPGA cores compatible with strict SWaP constraints of 5th generation tactical aircraft. The Phase I Option, if exercised, will culminate in a Preliminary Design Document (PDD). This document will detail the finalized architectural constraints, interface control definitions, and a hardware-software roadmap required to transition the design into a functional prototype in Phase II.
The Phase I effort will include prototype plans to be developed under Phase II.
PHASE II: Develop, integrate, and demonstrate a full-scale prototype of Parallel Multi-Core Sensor Fusion architecture. Building on Phase I architectural design and simulation results, the software-defined fusion algorithms will be transitioned into a tactical-grade processing unit. The primary focus of this effort is the real-time execution of fused track correlation across multiple sensors (both heterogeneous and homogeneous) data streams without the latency overhead inherent in legacy serial processors.
Technical Milestones include:
Hardware-in-the-Loop (HiTL) Integration: Implement the parallelized fusion engine onto a multi-core System-on-Chip (SoC) that meets the 28V DC power and 80-pound weight constraints.
Algorithmic Optimization: Refine sub-task decomposition to ensure balanced load distribution across processing cores, targeting an approximate reduction in end-to-end track latency of 50% compared to Phase I benchmarks.
Performance Demonstration: Conduct a demonstration using sensor data to validate track consistency and correlation accuracy under dynamic, complex scenarios.
The final Phase II deliverable will be a Technology Readiness Level (TRL) 6 prototype, including a comprehensive Test and Evaluation (T&E) report and a transition plan for integration for Program Offices and manned/unmanned platforms.
Work in Phase II may become classified. Please see note in Description section.
PHASE III DUAL USE APPLICATIONS: Integrate the Phase II developed processing unit within a HiTL simulation, verify the performance of the complete system, and transition to an aircraft platform. Examples of potential dual use applications include search and rescue, home/private security, autonomous driving/robotics, and smart grid/energy management.
REFERENCES:
KEYWORDS: Parallel Processing; Sensor Fusion; Algorithmic Optimization; Target Tracking; Sensor Networks; Multi-Core Processors; Situational Awareness; Sensor Processing
TPOC 1 : Anthony Reid
(301) 000-0000
anthony.p.reid9.civ@us.navy.milTPOC 2 : Kristina Rickard
(240) 572-6625
kristina.r.rickard.civ@us.navy.mil
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