DON26TZ05-NV023 TITLE: Detection and Classification of Low Probability of Intercept radar waveforms using Field-Programmable Gate Array with Cognitive Techniques

OUSW (R&E) CRITICAL TECHNOLOGY AREA(S): Quantum and Battlefield Information Dominance (Q-BID)

COMPONENT TECHNOLOGY PRIORITY AREA(S): Microelectronics

PROJECTED CMMC LEVEL REQUIREMENT: Level 2 (Self)

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. 

OBJECTIVE: Utilize a Digital Radio Frequency Memory (DRFM) Radio Frequency System-on-Chip (RFSoC) device’s Field-Programmable Gate Array (FPGA) to develop an advanced electronic warfare cognitive capability that detects advanced Low Probability Intercept (LPI) waveforms across a wideband frequency range.

DESCRIPTION: DRFMs are typically used to characterize and jam adversarial radar signals. Detecting and classifying LPI waveforms with low latency from adversarial sources is critical to DRFM effectiveness, enabling optimization of jamming countermeasures based on the identified radar type.

Detecting and classifying LPI radar signals is non-trivial and requires significant computing power. Because LPI signals are typically low power, high duty cycle, and wideband, they require long integration times and high receiver sensitivity. While these Radio Frequency (RF) considerations are fundamental challenges in LPI detection, this effort will focus on signal processing techniques for LPI detection and implementation on a FPGA, with emphasis on detection methods.

Traditional signal processing methods include, but are not limited to, adaptive matched filtering with Fast Fourier Transform (FFT) frequency detection, various filter banks, autocorrelation, Wigner-Ville distribution, and cyclostationary processing. Leveraging FPGA technology may provide performance gains through more advanced cognitive techniques such as time-frequency analysis, convolutional neural networks (CNNs), and deep learning methods including long short-term memory (LSTM) networks. In fact, the FPGA is the ideal tool for this, since its hardware emulation of algorithms allows for real-time or near real-time performance.

DRFM RFSoCs targeted for Test and Evaluation (T&E) threat-representative flight systems can be retrofitted with this capability, as FPGAs can adapt hardware description language (HDL) from other implementations. Implementing this system on a DRFM platform presents challenges due to HDL requirements and the relatively recent adoption of direct-RF architectures to access wide frequency ranges.

The Airborne Threat Simulation Organization (ATSO) at the Naval Air Warfare Center, Weapons Division (NAWCWD), Point Mugu, California, is responsible for simulating real adversarial threats for Navy training. ATSO has access to extensive LPI waveform data that can support training, testing, and validation of deep learning algorithms, convolutional neural networks, or other knowledge-based techniques. Leveraging this a priori knowledge, the research institute point of contact, will identify, optimize, and develop cognitive algorithms suited to ATSO applications. If multiple algorithms are identified, they may be implemented in parallel.

Because real-time hyperparameter adjustment on the FPGA is not practical, neural network or cognitive techniques must be designed and trained on a high-compute PC or Linux platform, if required. Other algorithms not dependent on deep learning or cognitive techniques can be developed in hardware description language (HDL) and behaviorally simulated using software such as ModelSim. Benchmarking development metrics should be straightforward, as ATSO can provide ground truth data.

An evaluation kit of the Advanced Micro Devices (AMD) (formerly Xilinx) RFSoC is proposed to prototype this capability. The final deliverable will be a report assessing the feasibility and effectiveness of implementing advanced cognitive techniques on RFSoCs.

PHASE I: Compile a large database to train and validate a conceptual model. (Note: this database can be developed using numerical computation software such as MATLAB.) Identify algorithms.

Demonstrate algorithm feasibility prior to deployment on an RFSoC platform.

Provide prototype plans to be developed under Phase II.

PHASE II: Develop additional HDL to implement the required signal processing functions. Create testbenches to measure model performance as it transitions from simulated environments (MATLAB and ModelSim) to the hardware design environment in Xilinx Vivado.

Conduct sufficient HDL validation and then deploy the design to the Xilinx RFSoC. Transmit LPI waveforms provided by the ATSO to the RFSoC using Keysight or other RF instrumentation in a laboratory benchtop environment for initial testing. The RFSoC and associated algorithms it was programmed with shall be delivered as the project’s prototype.

Conduct testing to further validate system performance using facilities maintained by NAWCWD, Point Mugu. Transmit LPI waveforms over the air in an anechoic chamber to evaluate detector performance under controlled conditions.

Note: If additional funding becomes available, the DRFM detector and classifier may be integrated onto targets such as the GQM-163A to enhance live, virtual, constructive training realism. This effort would require systems engineering support to integrate the LPI detector into a flight-capable module within the space constraints of the target platform.

PHASE III DUAL USE APPLICATIONS: Finalize the hardware and firmware design for integration into a target platform such as the GQM-163A or other operational systems. Ruggedize the Phase II prototype for the intended operational environment.

Conduct comprehensive Operational Test and Evaluation (OT&E) in live, virtual, and constructive (LVC) training scenarios to validate system performance against a broad range of threats. Develop a transition plan and manufacturing process to support wider fleet deployment. Provide lifecycle support documentation for system maintenance and future algorithm updates.

This technology has significant dual-use potential in any application requiring the detection of weak or complex signals in a crowded electromagnetic spectrum. Commercial applications include:

• Telecommunications: Cognitive radio systems could use this technology to dynamically sense and adapt to spectrum usage, improving network efficiency. Techniques from this technology could also be applied to the cell phone industry, to improve links to cell towers even when in a low signal environment.

• Automotive: Advanced driver-assistance systems (ADAS) and autonomous vehicles could leverage these techniques to enable the detection and classification of radar signals from other vehicles and infrastructure, enhancing safety and reliability.

• Spectrum Monitoring: Government regulatory bodies and private companies can use this for identifying unlicensed or interfering signal sources.

• Scientific Research: Applications in radio astronomy and atmospheric sensing, where detecting faint signals in significant noise is a primary challenge.

REFERENCES:

1. Denk, A. "DETECTION AND JAMMING LOW PROBABILITY OF INTERCEPT (LPI) RADARS." Naval Postgraduate School, Thesis, September 2006. https://apps.dtic.mil/sti/tr/pdf/ADA456960.pdf
2. Lawrence, D.E. "Low Probability of Intercept Antenna Array Beamforming." IEEE Transactions on Antennas and Propagation, vol. 58, no. 9, pp. 2858-2865, Sept. 2010. doi: 10.1109/TAP.2010.2052573 https://ieeexplore.ieee.org/document/5484594

KEYWORDS: Low Probability Intercept; LPI; Electronic Warfare; Field-Programmable Gate Array; FPGA; RFSoC; Machine Learning; Signal Processing; Digital Radio Frequency Memory; DRFM; Radio Frequency System-on-Chip

TPOC 1 : Jonathan Chhang
(805) 989-8795
jonathan.m.chhang.civ@us.navy.mil

TPOC 2 : Kelvin Ramos
(805) 989-8795
kelvin.e.ramos.civ@us.navy.mil